FED conference 2021 in Bamberg, Germany
The next eCADSTAR presentation will take place from September 16th-17th 2021, at the FED conference in Bamberg, Germany.
Come meet us at the FED Conference 2021 in Bamberg, Germany!
Join us at Welcome Kongresshotel situated in Bamberg, Germany, on 16th-17th September, where eCADSTAR will be presenting to everyone. We are looking forward to showcasing our topic and afterward exchanging ideas in regard to sustainability in PCB Design, as well as attending the other 50+ lectures on the current industry topics, over the course of the 2 days.
The highly knowledgeable Ralf Brüning will educate the FED Conference on ‘The fast analysis of the current load of power supply vias‘ in PCB Designs. The talk will be held on September the 16th at 11.20 am at the Bamberg event, and is one lecture that shouldn’t be missed!
Where to find us
As well as presenting at the FED Conference, there will be the chance to speak to our technical experts from the Zuken and CSK / eCADSTAR teams at booth 17 to find out more about the processes and solutions we develop to overcome difficult challenges and obstacles in PCB design, sustainability, and beyond.
There will be a live demonstration of the eCADSTAR EDA software that will showcase:
- What’s new for eCADSTAR in the v2021.1 update
- The eCADSTAR Schematics and SPICE controller
- eCADSTAR 3D PCB Design & Creepage/ Clearance Checks + more
Should you be interested to learn more about our presentation or want to speak to us, be sure to register down below!
Background information on the fast analysis of the current load of power supply vias
Technology trends such as increasing performance (and thus increasing power consumption and higher currents) of modern CPUs/MPUs, DSPs, and also SoCs/FPGAs, as well as smaller designs/form factors (e.g. IoT/IIoT applications), are also causing design problems and physical effects in the conventional design process of digital circuit boards, which were previously found almost exclusively in power electronics.
These issues have been taken into account for several years with power integrity simulation tools available on the market. However, practical experience shows that such tools are used only very rarely – also because the developers often overestimate the preparation and modelling effort required for meaningful use of power integrity simulation, fearing that the simulation is ‘too complex’.
Often questions of current of lines and vias are still treated on the basis of IPC tables and analytical investigations or worst-case estimations instead of solving them by simulation on the virtual prototype.
In this presentation, an actual DDR4 board is used to practically study the current levels, IR drop, and current flow occurring in the vias of a power supply system. Using various parametric studies (different vias, change of diameter), the concrete effects of alternative design measures on the current distribution and ultimately on the quality of the power supply are investigated. Special focus is put on a tool-neutral presentation of the easy usability of such simulation tools.
View more information about the FED Conference on the CSK website here.