High-Speed PCB Design

Manual and automatic editing tools enable nets to be tuned precisely for track length or flight-time to achieve optimum timing characteristics


With its highest performing routing tool, eCADSTAR offers specific functionality targeted for high-speed PCB design, such as DDR2, DDR3, DDR4 and PCI Express, including min/max length, skew, delay and crosstalk limits to meet tight timing and noise margins.

Overlooking a high-speed circuit creates signal chaos


You have to design the routing topology of your high-speed PCB carefully—trace geometry, layer stack, materials and electromagnetic coupling—or else signals will be degraded or dysfunctional.

This can apply to any part of a circuit board. Many standards, including the commonest memory circuits, PCI Express and USB, require high-speed PCB layout and routing.

Selected areas—or even signal layers—of a PCB, often must be treated as high-speed, even if the rest of the PCB does not.

High-speed design means concern for signal integrity. Treating high-speed signals as travelling waves. Making the paths they take as smooth as possible in electrical, not just physical, terms. You can optimize your PCB design for maximum resilience, going beyond basic design rules and guidelines such as trace length, trace width, and component placement.

High Speed Signal PCB design interpretation

PCB of High speed design

Figure 1: Placement replication on a second high-speed port

Cabling of high speed design

Figure 2: Automatic, no-constraint, node-to-node length matching for a DDR4 byte lane

Design epic high-speed PCBs with minimum setup


eCADSTAR offers specific features for high-speed PCB design, such as DDR3, DDR4, and PCI Express. These include topology, min/max length, skew, delay and crosstalk limits to meet tight timing and noise margins. But you do not always need constraints to make progress. eCADSTAR works with you to get real-world results in the quickest possible way. For example, you can:

  • Copy relative placement or routing between similar channels and share it with other designers, eliminating reimplementation errors and making design upgrades much easier and more consistent
  • Automatically match node-to-node lengths with no need to set constraints—a real timesaver for matched signals such as byte lanes and address/command buses

Quick, accurate, on-cursor high-speed topology control


Set up standard topologies like “Fly-by” quickly and easily in eCADSTAR PCB Editor. Choose from a wide selection of built-in topology templates with instant visualization. And route with Virtual Branch Points as a guide.

Holistic view of PCB design eCADSTAR of High speed circuit

Figure 4: Topology template with constraints, applied to a DDR4 differential clock, contrasting with lowlight view in PCB Editor

eCADSTAR Schematic Editor Menus detailing high speed design

Figure 3: Minor relative length differences shown in Constraint Browser for a DDR4 bus 

Set constraints, design to them, analyze, verify—just one GUI style


Constraints serve two main purposes: checking that your design conforms to them and designing with them for correct-by-construction. eCADSTAR works with you, whatever your approach. Maybe you want to set constraints in the schematic, where you can see what the circuit is doing. Maybe you want to do that during PCB design. Constraint Browser is built into both eCADSTAR Schematic Editor and PCB Editor and the user interface is the same.

Control length, delay, and skew—and you don’t always need constraints


With standards-based buses such as DDR4 and PCI Express, there’s no leeway to scatter vias amongst buses at random. Length-based constraints are often the best way to route, keeping length differences (skew) very small or zero and/or keeping absolute length within tight margins.

You can set constraints in terms of delay too. This works well if application notes express constraints like that, or if the path from source to load isn’t uniform. You can combine automatic lengthening to constraints with no-constraint node-to-node lengthening. That can be more efficient – for instance matching DQ byte lanes and ADDRESS/CMD signals without constraints, before lengthening differential CK and DQS signals relative to them, controlled by constraints.

PCB circuit in eCADSTAR - high speed design

Figure 5: Clock and strobe signals, indicated by the arrows, can be lengthened to relative skew constraints after associated buses have been length-matched 

High Speed design analysis in eCADSTAR

Figure 6: Consistent constraints, analysis and results 

Analyze, simulate and verify with best-in-class consistency


Choose what you need from the large range of simulation and analysis features in eCADSTAR bundles. High-speed simulation GUI style is consistent throughout eCADSTAR. Set up design scenarios before even starting physical design and see how they compare after placement, routing, and detailed component choice.  

Include Power Integrity/EMI simulation to check DC and AC power distribution in detail and optimize critical design features like plane geometry and decoupling. 

Or you can include the SPICE simulation interface, driving industry-standard LTspiceTM to simulate analog circuits directly from your design data. 

Control single-ended and differential impedance


Single-ended and differential impedance control are fundamental to high-speed design, even if constraints only apply to selected PCB areas.

eCADSTAR automatically derives widths and spacings to meet your impedance constraints, but if you prefer, you can set those directly. You may decide to do that to match a PCB manufacturer’s recommendations instead of calculating value PCB manufacturer’s recommendations can be stored in your technology and design rule shared with other designers and re-used in future designs.

High speed PCB design Impedance Control

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