Signal Integrity Analysis in PCB Design

EMBEDDED SIGNAL INTEGRITY ANALYSIS

Signal integrity analysis is embedded into the eCADSTAR Schematic and PCB Editors providing pre-layout and post-layout simulation capabilities.

• Simulate, measure, share results independently of PCB design.
• Constrain and plan topologies in the pre-layout phase.
• Plan impedance using the integrated field solver using lossy interconnect models.
• Analyze signals in the time domain.
• Automatic measurement for key distortion and timing parameters (e.g. slew rate) allows fast error detection.

SIGNAL INTEGRITY ANALYSIS ADVANCED

Signal integrity analysis advanced for very high-speed design. Builds on the functionality that the Signal Integrity option delivers and adds even more functionality.

• Derive S-parameters for topologies that you have extracted and edited in Electrical Editor.
• S-Parameters allow modeling passive interconnect behavior in frequency-domain (derived from measurement or like in eCADSTAR by simulation). S-Parameter export from the Electrical editor handles modeling of passive circuit elements only.
• S-Parameters describe coupling and transmission behavior of a system for a wide frequency range. Issues at high frequencies which for example may cause crosstalk can be identified, quickly.
• TDR (Time-Domain-Reflectometry) analysis sends a fast pulse down the PCB trace and displays the returning reflections, which indicate changes in impedance. This allows estimating signal integrity performance without the need to have IBIS buffer models assigned.

S-PARAMETER RESULT (MAGNITUDE AND PHASE)