Designing High-Speed PCBs in a Connected World

An electronic engineer’s take on eCADSTAR and how it works in a connected world.

PCB design has changed: more mixed, more connected.

re-usable data pcb design
Figure 1: Joined-up PCB design

The idea of a “low-speed” and “high-speed” divide is pretty dated – especially with the growth of Internet of things (IOT). We have to make sure all the diverse stuff on a PCB works in harmony.

The way we’ve been routing high-speed digital boards works because we do it in a certain style: reference planes, differential pairs, impedance control. All this shapes the electric and magnetic fields so we can predict how they’ll behave. Do something different and all bets are off.

Digital signals now fly so fast that we have to treat the whole thing as a 3D problem from start to finish. All this applies to RF and then some, because RF works outside many of the assumptions we make for the rest. It can get weird. If you have wireless connectivity, then you have RF.

But we can do it, because these boards are assemblies of signaling systems. There are known-good rules for laying out each system, provided you apply the right rules to the right design.

I’m an electronic/software engineer with, frankly, rudimentary PCB layout skills. Amongst other things, I like to throw new tech at new features and see what happens. eCADSTAR high-speed is new as I write this, so here is my take on what it does for you.

DDR4: It isn’t a DIMM card, or is it?

First, I checked out the JEDEC standard. It’s free once you create an account. Very thorough guidelines if you’re designing a memory card. I’m mounting directly on-board, but how do electrons know that? They don’t; theirs is a world of impedance and electric and magnetic fields.  Provided I have the space to follow the same guidelines, I can design a rock-solid bank of SDRAM. The benefits run even deeper, but I’ll come to that. I can’t repeat the JEDEC guidelines here because they are copyright, but I can show you what I did.

First, topology.

When you lay DDR4 out like a DIMM card, it needs just two basic single-ended and differential topologies: Point-to-Point and Fly-by. Those and a lot more are standard eCADSTAR templates, so I flipped through the previews,  picked the ones I wanted and applied them to my memory signals.

JESD79-4B SDRAM eCADSTAR design data
Figure 2: Applying topology templates with preview

I set up skew (relative) and absolute length constraints. JEDEC guidelines apply when you space the SDRAMs in a particular way, so that’s what I did.

And then I routed to those topologies.

I’ve never laid out PCBs for a job, but on the other hand, I’ve done IC design and I’m an optimizer. Have those SDRAM designers done anything to help with routing? You bet they have! They’ve laid out the package balls so you can route to zero SDRAM to SDRAM skew on 4 layers. I fanned out all the SDRAMS identically then I routed one set from package to package and copied and pasted it to the others.

SDRAM -Constraint Browser eCADSTAR
Figure 3: Zero-skew routing between SDRAMs

I had to equalize lengths between the SDRAMs and their controller, so I lengthened to constraints interactively before checking it all in Constraint Browser. Zero skew all the way, so long as I paid attention to routing channels and did some pin swapping at the controller.

Figure 4: Lengthening between controller and first SDRAM

RF: It’s high-speed and then some

I wanted a satellite-tracking antenna on the same board. There are exacting routing requirements: Federal Communications Commission (FCC) regulations and other really serious stuff that makes sure wireless signals don’t jam military and aerospace systems.

The routing is quite wide and it’s shape-based. Plain old tracks won’t do. The track is surrounded by ground in a specific style. Below it is a cavity through ground on the next layer and finally its main reference ground on the third layer, yielding characteristic impedance of 50Ω.

eCADSTAR Antenna_Route_3D
Figure 5: Routing a satellite-tracking antenna

I used eCADSTAR’s comprehensive shape-creation tools to get this right. The shapes I used aren’t just shapes, they’re templates. Once you get used to templates, they’re fantastic, because they adapt right away when you change anything inside their area, like vias or plough-through tracks. Much better than plain old copper areas.

Why I like eCADSTAR high-speed

I guess one reason is that I work for Zuken, so I’d have some explaining to do if I didn’t like eCADSTAR. But I like it, I really do.

I particularly like that it’s consistent. R&D thought it through at this time and for this connected, high-speed, RF world. They haven’t had to nail on new features that don’t fit comfortably with how the product was conceived.

Library editor works like Schematic Editor and PCB Editor. You do stuff in the place you’d expect. Online library parts just merge right in, including their 3D models, but once merged in, they’re adaptable too. For example, you may want to change some schematic symbols to fit with how you work, and that’s fine and it’s easy. I wanted mine filled and I wanted to edit them a bit to show what they are, because I knock this stuff together for articles like this where’s that’s important.

About the Author

Jane Berrie
Jane BerrieSignal Integrity Expert, Zuken Tech Center, Bristol.
Jane Berrie has been involved in EDA for PCB signal integrity since the 1980s. Her articles have appeared in many publications worldwide - too many times to mention. Jane is also a past session chair for 3D IC design at the annual Design Automation Conference. Jane’s also an innovator with a unique perspective, who constantly works on new solutions in the fast-evolving world of electronic design. In her spare time, Jane has organized themed charity events - including two in aid of lifeboats and red squirrel survival. Jane is also a regular disco-goer.


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