FED Conference 2025

The 33rd FED Conference on September 24 and 25 in Lübeck is the only German-language event that covers the entire development and manufacturing process of electronic assemblies and devices.

The numerous specialist presentations, expert panels and inspiring keynotes, some of which will also be held in English, complement the accompanying trade exhibition. This allows participants to find out about current industry trends, gain new perspectives and learn from each other. Participants can also talk to us about the latest eCADSTAR developments throughout the event.

Focus 2025: Practical strategies for design and production

The motto of this year’s 33rd FED Conference is: “Design and production of printed circuit boards and assemblies – perspectives, strategies and solutions for practice” and is aimed at all printed circuit board and assembly designers, production specialists, process and quality managers and decision-makers from commercial areas. Consequently, technologies, processes and best practices are brought together.

Zuken, eCADSTAR and CSK will be on stand 2 this year. As part of the two-day FED conference, we will be demonstrating the new features of eCADSTAR Version 2025 live and showing useful approaches of the TRM3 software from ADAM Research and the PCB Footprint Expert software from PCB Libraries.

Technical presentation by Zuken: Mastering DDR4/DDR5 design

For those interested, Mr. Karl-Heinz Kluwetasch from CSK will be happy to give you more information about the event and the possibilities it offers. The conference provides a valuable opportunity to network with like-minded professionals. In addition, Mr. Ralf Brüning from Zuken will address the design challenge of 4th and 5th generation DDR storage systems in his presentation on September 24th:

“Ever faster, ever more complicated – challenges of modern memory and data interfaces and practical approaches to solving them”

Developers of modern assemblies are now faced with demanding challenges. Fast data interfaces as well as fourth and fifth generation memory technology (DDR4/DDR5) are also finding their way into the industrial electronics and automotive sectors.

The data rates (6400MT/s and higher) with large bandwidths, falling voltage levels of less than one volt (LPDDR5) and rise/fall times in the range of significantly less than 100ps together with the large number of signals that are subject to corresponding rules (impedances, signal quality, length and timing relations (skew), blocking and power integrity, etc.) require precise layout and extensive assurance of signal and power integrity.

Careful planning of the layout (layer structure/technology) and the definition of the design rules (constraining) are the first, often decisive steps towards a successful design. The layout guidelines of the IC manufacturers (memory controllers) and the standardization organizations (JEDEC, USB, PCIe, etc.) form the basis for this process.

Using real applications (DDR3/DDR4/DDR5) as an example, we will show what developers and layout designers need to consider in order to meet these requirements.

More info and registration

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